Analysis of System Bus Transaction Vulnerability in SystemC TLM Design Platform

As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. The system bus, such as AMBA AHB, provides an integrated platform for IP-based SoC. Apparently, the robustness of system bus plays an important role in the SoC reliability. In this study, we propose a useful bus system vulnerability model and present a thorough analysis of system bus vulnerability in SystemC transaction-level modeling (TLM) design level by injecting faults into the bus signals, which can assist us in predicting the robustness of the system bus, in locating the weaknesses of the bus system, and in understanding the effect of bus faults on system behavior during the SoC design phase. The impact of benchmarks on system bus vulnerability is also addressed. The contribution of this work is to promote the dependability verification to TLM abstraction level that can significantly enhance the simulation performance, and provide the comprehensive results to validate the system bus dependability in early design phase for safety-critical applications.